3. PCB Design

Learning Objectives

• Explain what a printed circuit board (PCB) is and how PCB design fits between schematic capture and manufacturing
• Describe the key stages of PCB design: layer stackup definition, component placement, routing, and design rule checking
• Identify the main factors that drive component placement decisions (thermal, signal integrity, mechanical)
• Explain why multilayer boards use dedicated power and ground planes
• Apply basic routing best practices (trace width, clearance, via usage) to a simple board
• Compare popular PCB design tools (Altium Designer, Cadence Allegro/OrCAD, KiCad, Eagle)

Quick Answer

PCB design is the process of translating an electrical schematic into a physical, manufacturable circuit board — deciding where each component sits, how many copper layers the board needs, and how copper traces route signals and power between components while meeting electrical and mechanical constraints. It matters because a schematic that is logically perfect can still fail in the real world if the physical layout introduces noise, excessive heat, or manufacturing violations; PCB design is where abstract connectivity becomes a physical object that must survive real electrical, thermal, and mechanical conditions. Every physical electronic product — from a smartwatch to a satellite — depends on PCB design done in tools like Altium Designer, Cadence Allegro, or the open-source KiCad.

From Netlist to Copper: The PCB Design Flow

PCB design takes the netlist produced by schematic capture and turns it into a fabricable object. The flow is sequential but iterative — issues found late (signal integrity, thermal, DRC) frequently send you back to placement or even the schematic.

Layer Stackup

A PCB is built from alternating layers of copper and insulating substrate (typically FR-4 fiberglass). A simple hobby board might be 2-layer (top and bottom copper only), while a smartphone motherboard can have 10+ layers. More layers mean more room for routing and dedicated power/ground planes, at higher manufacturing cost.

• Signal layers carry traces that route specific nets between components.
• Power and ground planes are solid (or near-solid) copper layers dedicated to distributing supply voltage and providing a low-impedance return path for signals — critical for both power integrity and signal integrity on any board running above a few MHz.
• Layer stackup order matters: placing signal layers adjacent to a ground plane (not adjacent to another signal layer) reduces crosstalk and gives high-speed signals a clean, close return path.

Component Placement

Placement is not just "where there's room" — it's an optimization problem balancing several competing constraints:

• Signal integrity — place time-critical or high-speed components close together to minimize trace length (and therefore delay and radiation).
• Thermal management — place high-power components (voltage regulators, power transistors) with room for heat sinks or thermal vias, and away from heat-sensitive parts like precision analog sensors.
• Mechanical constraints — connectors need to align with an enclosure's cutouts; mounting holes must clear component keep-out zones.
• Manufacturing/assembly — components should be oriented consistently where possible to simplify automated pick-and-place assembly.

Routing

Routing is drawing the actual copper traces that realize each net from the netlist. Good routing follows several principles:

• Trace width is chosen based on the current the trace must carry (a 0.2 mm trace might be fine for a logic signal but would overheat carrying 2 A of motor current) — engineers use tools or IPC-2221 charts to size power traces correctly.
• Clearance (spacing between traces/pads) must meet the manufacturer's minimum, and higher voltages require larger clearances to prevent arcing.
• Vias connect traces between layers; excessive vias on a high-speed signal path add inductance and can degrade signal integrity, so are minimized on critical nets.
• Differential pairs (USB, HDMI, Ethernet) must be routed with matched length and controlled spacing to preserve signal timing and reject common-mode noise.

Real-World Example: A High-Speed Data Acquisition Board

Imagine laying out a board with an ADC (e.g., MCP3008), a microcontroller, and several sensors, targeting a 1 kHz sample rate with minimal noise. You'd place the ADC close to the sensors to keep analog signal traces short (minimizing noise pickup), route those analog traces away from switching digital lines and power traces, use a solid ground plane beneath the analog section to keep the reference stable, and separate power domains (5V digital, 3.3V analog) with careful plane splits or ferrite bead filtering. After routing, DRC verifies trace widths, clearances, and via sizes all meet the fabricator's minimum feature specifications before Gerber files are generated.

Why It Matters

A perfectly correct schematic routed carelessly can still fail: analog signals corrupted by nearby switching noise, a power trace that overheats under load, or a board that simply can't be manufactured because trace spacing is below the fabricator's capability. PCB design is where theoretical circuit correctness meets physical, thermal, and manufacturing reality — and it's frequently where subtle, hard-to-debug field failures originate.

Key Terms

Term	Definition	Related Concept
PCB (Printed Circuit Board)	A board of insulating substrate and copper layers that mechanically supports and electrically connects components	Layer stackup
Layer stackup	The defined arrangement of copper and insulating layers in a PCB	Signal layer, plane
Power/ground plane	A solid copper layer dedicated to distributing supply voltage or providing a return path	Power integrity
Trace	A strip of copper that electrically connects two points on a PCB	Routing, net
Via	A plated hole connecting traces on different layers	Multilayer routing
Clearance	The minimum spacing required between copper features to avoid shorts/arcing	Design rules
Differential pair	Two traces carrying complementary signals (e.g., USB D+/D-) routed with matched length and spacing	Signal integrity
Gerber file	The industry-standard file format describing each PCB layer for fabrication	Manufacturing output
Silkscreen	The printed layer showing component outlines, reference designators, and labels on the board	Documentation

Common Mistakes

Misconception: As long as every net from the schematic is routed, the PCB layout is "done" and correct. Why it's wrong: Routing completeness only guarantees electrical connectivity matches the netlist. It says nothing about whether trace widths can handle the current, whether high-speed signals maintain integrity, whether the board will run too hot, or whether it can even be manufactured within the fabricator's tolerances. Correct understanding: A finished layout must also pass DRC, meet current-carrying requirements, and — for sensitive designs — pass signal integrity and thermal analysis before it's ready for fabrication.

Misconception: More copper layers always make a design better. Why it's wrong: Additional layers increase manufacturing cost and lead time significantly, and for a simple, low-speed design they add no real benefit. The right layer count is the minimum that satisfies routing density, power integrity, and signal integrity requirements — not the maximum available. Correct understanding: Layer count is a deliberate engineering trade-off between routing/performance needs and cost/complexity, decided early based on design requirements.

Misconception: Trace width doesn't matter much as long as the connection is made. Why it's wrong: Traces have finite resistance and current-carrying capacity; an undersized trace carrying significant current will heat up, potentially degrading or even burning the board, and can cause unacceptable voltage drop along power distribution paths. Correct understanding: Trace width must be sized to the expected current (using standards like IPC-2221) for power and high-current nets; signal traces are usually sized for controlled impedance rather than current capacity.

Comparison and Connections

Feature	Altium Designer	Cadence Allegro/OrCAD	KiCad
Typical use case	Commercial multilayer boards	Enterprise, high-layer-count, high-speed boards	Hobbyist, academic, open hardware
Cost	Commercial subscription	Commercial, enterprise-tier pricing	Free, open-source
Autorouting quality	Strong, with interactive length-tuning	Very strong, industry standard for complex boards	Basic autorouter, mostly manual routing preferred
3D visualization	Built-in	Built-in (via Allegro/Sigrity integration)	Built-in (3D viewer)
Best suited for	Professional consumer electronics	High-layer-count enterprise/telecom boards	Prototyping, education, small-to-mid complexity boards

Practice Questions

Recall

1. What is the input to the PCB design process, and what are the two main output files generated at the end? Guidance: Input is the netlist from schematic capture; outputs are Gerber files (copper/silkscreen/solder mask layers) and drill files for hole/via locations.

2. Name two reasons a PCB might use a dedicated ground plane rather than routing ground as a regular trace. Guidance: A ground plane provides a low-impedance return path for signals (improving signal integrity) and helps distribute current without significant voltage drop or noise (improving power integrity).

Understanding

3. Explain why component placement decisions must balance signal integrity, thermal, and mechanical constraints rather than optimizing for just one. Guidance: Optimizing purely for shortest traces might place a hot power regulator next to a heat-sensitive sensor; optimizing purely for thermal spacing might create excessively long high-speed traces. Real placement is a compromise across all constraints simultaneously.

4. Why must differential pairs (like USB D+/D-) be routed with matched trace lengths? Guidance: Differential signaling relies on both lines arriving at the receiver at (nearly) the same time so their difference can be correctly detected; a length mismatch introduces timing skew that degrades signal quality and can cause data errors at high speed.

Application

5. You are laying out a board with a switching power supply next to a precision analog sensor. Describe placement and routing decisions to minimize interference. Guidance: Physically separate the switching supply from the analog sensor, keep the analog section on its own quiet ground area, route noisy switching traces (and especially the switch node) away from and not over the analog ground/traces, and consider a ground plane split or careful stitching to control current return paths.

6. A fabricator's minimum trace clearance is 0.15 mm, but your design initially uses 0.1 mm spacing in a dense area. What should you do, and why does this matter? Guidance: You must adjust the layout to meet or exceed the fabricator's minimum clearance (0.15 mm), possibly by widening spacing, moving to a smaller component footprint, or adding a layer — violating manufacturing minimums risks shorts or outright fabrication rejection.

Analysis

7. Compare the design priorities for a 2-layer hobbyist board versus a 12-layer smartphone motherboard. Guidance: A 2-layer board prioritizes simplicity and cost, with limited routing flexibility and no dedicated planes; a 12-layer board dedicates multiple layers to power/ground planes and controlled-impedance routing, prioritizing signal integrity, EMI control, and dense component packing, at much higher cost and design complexity.

8. A board passes DRC but fails in the field due to a power trace overheating under sustained load. Analyze what step in the PCB design process was likely inadequate, and what should have been checked. Guidance: DRC checks spacing/geometry rules, not current-carrying capacity; the trace width for that power net was likely undersized for the actual current draw. A current-capacity check (IPC-2221 trace-width calculation) against real load conditions should have been performed during routing, not just a geometric DRC pass.

FAQ

How is PCB design different from schematic capture? Schematic capture defines the logical connectivity (what connects to what); PCB design defines the physical realization (where components sit and how copper traces route the connections). PCB layout must implement every net from the schematic exactly — it cannot add, remove, or change connections, only decide how to physically route them.

Why do some boards need more than two layers? Two layers (top and bottom) quickly run out of routing space on anything beyond a simple circuit, and offer no dedicated plane for stable power distribution or a clean return path for signals. Additional layers add routing capacity and dedicated power/ground planes, which become necessary as component density and signal speed increase.

What is a Gerber file and why is it the standard output? A Gerber file is a vector-based, layer-by-layer description of a PCB (copper patterns, solder mask, silkscreen) understood universally by PCB fabrication houses. It's the de facto industry standard because it lets any EDA tool's output be manufactured by any fabricator, regardless of which software produced the design.

Do I need to know soldering/manufacturing to do good PCB design? You don't need to be a hands-on assembler, but understanding manufacturing constraints (minimum trace/space, minimum via size, component footprint tolerances, reflow soldering thermal profiles) is essential — a design that ignores "design for manufacturability" (DFM) principles can be technically routable in software yet impossible or extremely expensive to actually build.

Can PCB design catch signal integrity problems automatically? Basic DRC checks geometry, not signal behavior. Catching genuine signal integrity issues (reflections, crosstalk, timing skew) requires dedicated signal integrity simulation tools that model trace impedance and electromagnetic behavior — this is a separate analysis step, typically run on high-speed nets after routing, not part of basic layout DRC.

Quick Revision

• PCB design converts a schematic's netlist into a physical board: layer stackup, placement, routing, and DRC
• Layer stackup determines routing capacity and whether dedicated power/ground planes are available
• Ground/power planes provide low-impedance return paths and stable power distribution — essential above a few MHz
• Component placement balances signal integrity (short critical traces), thermal (heat spreading), and mechanical (enclosure fit) needs
• Trace width must be sized for current-carrying capacity, not just "wide enough to look connected"
• Differential pairs (USB, HDMI, Ethernet) need matched trace lengths to avoid timing skew
• Routing completeness (all nets connected) does not equal a finished design — DRC, thermal, and signal integrity checks are still required
• Gerber files + drill files are the standard manufacturing output understood by all PCB fabricators
• Major tools: Altium Designer and Cadence Allegro/OrCAD (commercial, high-end), KiCad (free, open-source)
• More layers = more routing flexibility and better signal/power integrity, but higher cost — always a deliberate trade-off

Related Topics

Prerequisites: Schematic Capture, basic circuit theory, Ohm's Law

Related Topics: Layout Design, Design Rule Checking, Signal Integrity, Thermal Analysis

Next Topics: Layout Design, Design Rule Checking, Simulation and Verification