2. Schematic Capture

Learning Objectives

• Define schematic capture and explain its position as the entry point of the EDA design flow
• Identify the core components of schematic capture software: symbol libraries, nets, wires, and annotation
• Explain how a schematic becomes a netlist, and why the netlist (not the picture) is what downstream tools actually use
• Apply best practices for organizing, labeling, and documenting a schematic to avoid downstream errors
• Recognize common schematic capture mistakes that cause simulation or PCB layout failures
• Compare schematic capture tools (Altium, KiCad, Cadence OrCAD) at a high level

Quick Answer

Schematic capture is the process of drawing an electronic circuit as a diagram of standardized symbols (resistors, ICs, connectors) linked by wires representing electrical connections, using dedicated software rather than pencil and paper. It matters because the schematic is the single source of truth for everything that follows: simulation, PCB layout, and bill-of-materials generation are all derived from the netlist the schematic produces. A mistake in schematic capture — a missing connection, a wrong pin mapping, a mislabeled net — propagates silently into every downstream stage, which is why schematic capture is treated as a precision task, not just "drawing," in professional design. Tools like Altium Designer, Cadence OrCAD, and the free/open-source KiCad are the industry standards.

What Schematic Capture Actually Produces

It's tempting to think of a schematic as just a picture. It isn't. The real output of schematic capture is a netlist — a text-based list of every component, its pins, and which pins are electrically connected to which others. The graphical schematic is a human-readable representation of that netlist; the netlist is what the simulator and the PCB layout tool actually consume.

This is why a schematic that "looks right" but has a wire crossing another wire without a junction dot is a real bug — visually it might seem connected, but electrically it is two separate, unconnected nets. Schematic capture tools are precise about this distinction in a way a hand drawing never is.

Core Components of Schematic Capture Software

Every schematic capture tool, from KiCad to OrCAD, is built around the same handful of concepts:

• Component libraries — pre-built symbols for standard parts (resistors, op-amps, microcontrollers) with defined pin names, pin numbers, and electrical types (input, output, power, passive). Using an accurate library symbol matters enormously — a wrong pin-to-pin mapping in a library symbol will place a correct-looking schematic that is electrically wrong.
• Nets and wires — a "net" is a group of pins that must be electrically the same node. Wires are the graphical connections; net labels let you connect pins across the page without drawing a physical wire (common for power rails like VCC and GND).
• Reference designators and values — each component gets a unique identifier (R1, C3, U2) and a value (10kΩ, 100nF). These carry through to the PCB silkscreen and the bill of materials (BOM).
• Hierarchical sheets — for large designs, schematics are split into multiple linked sheets (e.g., "Power Supply," "MCU," "RF Front-End") connected by hierarchical ports, keeping each sheet readable.
• Electrical Rule Check (ERC) — an automated check for obvious schematic errors: unconnected pins, conflicting outputs driving the same net, missing power connections.

Why Schematic Capture Matters in the EDA Flow

Schematic capture sits at the very front of the design flow, which means every error here has maximum leverage — a wrong pin assignment discovered after PCB fabrication means scrapping boards, while the same error caught by ERC costs nothing but a few minutes.

• Design entry — it's the primary way a human communicates circuit intent to the EDA toolchain.
• Simulation preparation — the netlist generated from the schematic is what a SPICE simulator actually simulates; the schematic is the simulation model.
• Manufacturing preparation — the same netlist drives PCB layout, ensuring the physical board matches the intended circuit exactly, and the BOM for procurement is generated from component values and reference designators on the schematic.
• Documentation — a clean, well-annotated schematic is often the only reference future engineers (including future you) have for how a circuit works.

Real-World Example: Designing a Non-Inverting Amplifier

Suppose you're capturing a non-inverting op-amp amplifier with gain set by R1 and R2. In the schematic tool, you place an op-amp symbol (e.g., LM358) from the library, connect the input signal to the non-inverting pin, tie R1 between the output and inverting pin, and R2 between the inverting pin and ground. You label the power pins V+ and V- and connect them to global power nets rather than drawing wires across the whole sheet. Running ERC flags that pin 8 (an unused pin on a quad-op-amp package) is unconnected — a genuine warning, since floating CMOS inputs can cause instability, so you either tie it to a defined level or explicitly mark it as intentionally unconnected.

Common Challenges

• Learning curve — mapping mental circuit understanding onto a specific tool's library conventions and shortcuts takes practice.
• Complexity management — a design with hundreds of ICs needs disciplined use of hierarchical sheets and net naming, or the schematic becomes unreadable.
• Version control — schematic files are often binary or semi-structured, making diffing and merging harder than plain text code; teams increasingly use tools with Git-friendly file formats (KiCad's newer S-expression format is a deliberate move in this direction).

Best Practices

• Start with the power and ground distribution first — get every IC's power pins connected and decoupled before wiring signal paths.
• Use net labels/global labels for power rails instead of drawing long wires across sheets — it keeps the schematic readable.
• Name nets meaningfully (SPI_MOSI, not NET0032) so both the schematic and the PCB silkscreen/netlist are self-documenting.
• Run ERC early and often, not just once at the end — catching a floating input on day one is trivial; catching it after layout is not.
• Add text notes near tricky sections explaining why a value was chosen (e.g., "R7 sets bias current to 2mA per datasheet section 4.2").

Key Terms

Term	Definition	Related Concept
Schematic capture	Creating a circuit diagram of standardized symbols connected by wires, using dedicated software	Netlist
Netlist	A text list of components and the electrical connections (nets) between their pins	Schematic capture, PCB layout
Net	A group of pins/points that are electrically the same node	Wires, labels
Component library	A collection of predefined symbols with correct pin names, numbers, and electrical types	Symbol, footprint
Reference designator	The unique identifier assigned to each component (e.g., R1, U3)	BOM
Hierarchical sheet	A sub-schematic linked into a larger design via hierarchical ports	Design organization
Electrical Rule Check (ERC)	Automated check for schematic-level errors like unconnected pins or conflicting drivers	DRC (PCB equivalent)
Bill of Materials (BOM)	The list of every part, value, and quantity needed to build the circuit	Procurement
Global label / power symbol	A named connection point that links same-named nets across a sheet without a drawn wire	Net

Common Mistakes

Misconception: If two wires cross on the schematic, they are automatically connected. Why it's wrong: In every schematic capture tool, two crossing wires are electrically connected only if there is an explicit junction dot at the intersection. A crossing without a dot means the wires pass over each other without connecting — this is intentional, since real circuits need wires to cross without touching. Correct understanding: Always verify junction dots at intended connection points, and use ERC to catch cases where you meant to connect two nets but forgot the dot (or accidentally added one where you didn't want a connection).

Misconception: A schematic that looks visually correct is electrically correct. Why it's wrong: The schematic's appearance is a rendering of the underlying netlist; a wrong library symbol (with pins mapped to the wrong physical pin numbers) can look perfectly normal on screen while producing an incorrect netlist and therefore an incorrect PCB. Correct understanding: Always verify library symbols against the component's actual datasheet pinout, especially for custom or unusual parts, and cross-check the generated netlist, not just the picture.

Misconception: ERC (Electrical Rule Check) guarantees the circuit will work. Why it's wrong: ERC only checks structural/connectivity issues — unconnected pins, multiple outputs driving one net, missing power. It has no idea whether your resistor values give the right gain or whether your amplifier will be stable; that requires simulation and design analysis, not just rule-checking. Correct understanding: ERC is a necessary but not sufficient check. A clean ERC report means the schematic is structurally sound — it says nothing about whether the circuit is functionally correct.

Comparison and Connections

Feature	Altium Designer	KiCad	Cadence OrCAD
License	Commercial (subscription)	Free, open-source	Commercial
Typical user	Professional PCB teams	Students, hobbyists, small companies	Enterprise/analog-heavy design teams
Schematic-to-layout integration	Unified environment	Integrated (Eeschema + Pcbnew)	Integrated (OrCAD Capture + Allegro)
Scripting/automation	TCL, Delphiscript-like API	Python API	SKILL/Tcl
Best suited for	High-complexity, high-speed commercial boards	Learning, prototyping, open hardware	Legacy enterprise and analog-heavy designs

Practice Questions

Recall

1. What is the difference between a schematic and a netlist, and which one do downstream tools (simulators, layout tools) actually use? Guidance: The schematic is the visual diagram; the netlist is the text-based list of components and their pin-to-pin connections extracted from the schematic. Simulators and layout tools consume the netlist, not the picture.

2. Name three checks that an Electrical Rule Check (ERC) typically performs. Guidance: Unconnected pins, multiple output pins driving the same net, missing or floating power connections (any three of these, or similar).

Understanding

3. Explain why using global/net labels for power rails is preferred over drawing continuous wires across a large schematic. Guidance: Long wires across sheets clutter the diagram and are hard to trace visually; a net label lets any pin with the same label connect to the same net without a drawn line, keeping each sheet readable while preserving correct connectivity.

4. Why can a schematic "look correct" on screen but still generate an incorrect netlist? Guidance: If the library symbol's pin mapping doesn't match the real component's physical pinout (a bad or custom symbol), the rendered picture can appear normal while the underlying pin connections in the netlist are wrong.

Application

5. You're capturing a schematic for a microcontroller board with an SPI flash chip. Describe the steps you'd take, from placing the MCU symbol to generating a netlist ready for layout. Guidance: Place MCU and flash symbols from verified libraries → wire SPI signals (MOSI, MISO, SCK, CS) with meaningful net labels → connect power/ground and add decoupling capacitors → run ERC and resolve warnings → generate the netlist for PCB layout.

6. During ERC, you get a warning that an op-amp's unused input pin is "floating." Explain the risk and how you would resolve it. Guidance: A floating CMOS/op-amp input can pick up noise or settle at an indeterminate level, potentially causing oscillation or excess current draw; resolve it by tying the pin to a defined reference (ground, a bias voltage, or per the datasheet's recommended unused-pin handling).

Analysis

7. Compare the risk profile of an error caught by ERC during schematic capture versus the same logical error discovered only after PCB fabrication. Guidance: ERC-stage errors cost minutes to fix with no physical cost. The same error surviving into fabrication means scrapped boards, wasted assembly cost, and schedule delay — potentially a factor of 100–1000x more expensive to fix.

8. A team debates whether to use a monolithic single-sheet schematic or a hierarchical multi-sheet schematic for a 300-component board. Analyze the trade-offs. Guidance: Single-sheet is simpler for tiny designs but becomes unreadable and error-prone as component count grows. Hierarchical sheets improve readability and allow reuse of sub-circuits (e.g., a power supply block) across projects, at the cost of needing careful hierarchical port management to avoid connectivity mistakes between sheets.

FAQ

Is schematic capture the same as PCB layout? No. Schematic capture defines what is connected to what (the logical circuit); PCB layout defines where components physically sit on the board and how copper traces route between them. Schematic capture happens first and its netlist constrains what the layout tool is allowed to do — layout cannot add or remove connections, only realize them physically.

Can I skip schematic capture and go straight to PCB layout? Technically some very simple boards are laid out directly, but for anything beyond a trivial circuit this is a bad idea — you lose the netlist-driven consistency check between what you intended and what you built, and you lose ERC, simulation compatibility, and a clear document for future reference. Professional workflows always capture the schematic first.

Why do professional teams still care about schematic "style" (organization, layout of symbols on the page) if the computer only cares about the netlist? Because humans, not just the software, need to read and debug schematics — during design review, troubleshooting, or years later during a revision. A messy schematic with crossed wires and unlabeled nets is a maintenance and safety liability even if it produces a technically correct netlist.

What happens if two different net labels are accidentally given the same name? The schematic tool will treat them as the same electrical net, even if you intended them to be separate signals — this is a very common real-world bug. This is exactly why ERC and manual review of the netlist matter: silently merged nets don't throw an obvious visual error but will cause incorrect circuit behavior.

Do simulation models live in the schematic tool or somewhere else? It depends on the tool, but SPICE simulation models (transistor models, IC behavioral models) are typically attached to the library symbol as metadata. When you generate a netlist for simulation, the tool pulls in these attached models so the simulator knows how each component actually behaves, not just how it's connected.

Quick Revision

• Schematic capture is creating a circuit diagram of standard symbols connected by wires, using dedicated EDA software
• The real output is a netlist (component + pin connectivity list); the picture is a human-readable view of that netlist
• Core building blocks: component libraries, nets/wires, reference designators, hierarchical sheets, ERC
• Crossing wires are only connected if a junction dot is present — this trips up beginners constantly
• ERC catches structural errors (unconnected pins, driver conflicts) but says nothing about functional correctness
• The netlist from schematic capture feeds both simulation and PCB layout — it's the single source of truth
• Best practice: wire power/ground first, use net labels for rails, name nets meaningfully, run ERC frequently
• Errors caught during schematic capture are nearly free to fix; the same errors surviving to fabrication are very costly
• Major tools: Altium Designer and Cadence OrCAD (commercial), KiCad (free/open-source)
• A visually "correct-looking" schematic can still be electrically wrong if the library symbol's pin mapping is incorrect

Related Topics

Prerequisites: Introduction to EDA, basic circuit theory, component fundamentals (resistors, capacitors, op-amps)

Related Topics: PCB Design, Simulation and Verification, EDA Tools and Software

Next Topics: PCB Design, Layout Design, Design Rule Checking