6. Design Rule Checking

Learning Objectives

• Define Design Rule Checking (DRC) and explain why it exists as a distinct verification step
• Categorize DRC rules into geometric, electrical, and manufacturing/process rules
• Describe the typical DRC workflow: design preparation, rule definition, execution, and resolution
• Explain the relationship between DRC and other checks (ERC, LVS) in the overall verification flow
• Interpret a simple DRC violation report and identify a plausible fix
• Recognize the consequences of skipping or under-configuring DRC before fabrication

Quick Answer

Design Rule Checking (DRC) is an automated process that verifies a physical layout — a PCB or an IC — obeys the geometric, electrical, and manufacturing constraints set by the fabrication process before the design is sent for manufacturing. It matters because a layout can be logically correct (every net connected as intended) yet still be physically unmanufacturable or unreliable if, for example, two copper traces are spaced too closely, a via is too small for the fabrication process, or a trace can't carry its required current. DRC is the automated gatekeeper that catches these violations in software, where fixing them costs minutes, rather than in a fabrication run, where the same mistake can mean scrapped boards or a failed chip.

What DRC Actually Checks

DRC rules fall into three broad categories, and every fabrication process (a specific PCB manufacturer, or a specific silicon foundry node) publishes its own exact numeric limits for each:

• Geometric rules — minimum spacing between copper features, minimum trace/via width, minimum pad size. These exist because manufacturing processes have physical resolution limits; features closer together than the process can reliably produce risk shorting together or simply failing to form correctly.
• Electrical rules — maximum current density a trace can carry, minimum resistance/capacitance limits for certain structures. These exist to prevent traces or vias from overheating, degrading, or failing under normal operating current.
• Manufacturing/process rules — layer thickness constraints, material compatibility, and other process-specific limits tied to exactly how a given fabricator builds the board or chip.

How DRC Fits in the Verification Flow

DRC is deliberately narrow in scope — it only checks physical/geometric and electrical rule compliance, not whether the circuit does what you intended. That's a different check, called LVS (Layout Versus Schematic) for ICs, or a netlist-comparison for PCBs, which verifies the layout's connectivity actually matches the original schematic. DRC and LVS (or their PCB equivalents) are complementary: DRC asks "is this layout physically buildable and safe?" while LVS asks "does this layout actually implement the circuit I designed?"

The DRC Process

1. Design preparation — the design database is converted into a format the DRC tool can analyze, and relevant geometric/electrical data is extracted.
2. Rule definition — the specific numeric rules for the target fabrication process are loaded or configured (every foundry or PCB house provides its own rule deck).
3. Execution — the DRC engine scans the entire layout, checking every relevant feature against every applicable rule, and generates a report of any violations.
4. Resolution — the designer reviews violations and modifies placement or routing to fix them; some violations are genuine errors, others are false positives or acceptable exceptions the designer must judge case by case.
5. Verification — DRC is re-run after fixes, and the cycle repeats until the report is clean (or all remaining flagged items are explicitly, deliberately waived with justification).

Real-World Example: A Minimum Spacing Violation

Suppose a PCB fabricator's rule deck specifies 6 mil (0.15 mm) minimum trace-to-trace clearance, but a densely routed section of your board has two traces at 4 mil spacing. DRC will flag this as a violation before you ever send the design to fabrication. Left uncaught, this spacing might work on some fabrication runs and cause a short (or an intermittent failure from solder mask bridging) on others — DRC removes that gamble entirely by catching it deterministically, every time, before manufacturing.

Why DRC Matters

• Ensures manufacturability — prevents fabrication issues that would otherwise only surface during (or after) production, avoiding costly rework or scrapped units.
• Improves yield — catching subtle geometric violations early increases the fraction of manufactured units that work correctly.
• Standardizes practice — a shared, codified rule deck lets designers, manufacturers, and reviewers speak the same precise language about what's acceptable.
• Systematic quality assurance — replaces "eyeballing" a layout with a deterministic, repeatable, and complete check of every relevant feature.

Key Terms

Term	Definition	Related Concept
Design Rule Checking (DRC)	Automated verification that a layout obeys geometric, electrical, and manufacturing constraints	Geometric rules
Geometric rule	A DRC constraint on physical dimensions, such as minimum spacing or trace width	Manufacturability
Electrical rule	A DRC constraint on electrical properties like maximum current density	Reliability
Rule deck	The complete set of numeric DRC rules specific to a fabrication process or foundry	DRC execution
LVS (Layout Versus Schematic)	The check confirming a layout's actual connectivity matches the intended schematic/netlist	DRC (complementary)
Violation report	The output of a DRC run listing every rule violation found, with its location	Resolution
Yield	The fraction of manufactured units that function correctly	Manufacturability
Design-for-manufacturability (DFM)	Designing with fabrication constraints in mind from the start, reducing DRC violations	DRC

Common Mistakes

Misconception: DRC verifies that the circuit works correctly, not just that it's physically buildable. Why it's wrong: DRC only checks physical/geometric and electrical rule compliance against the fabrication process's constraints. It has no concept of your circuit's intended function — a completely wrong circuit that happens to have correct spacing and trace widths will still pass DRC cleanly. Correct understanding: DRC answers "can this be manufactured reliably?" — functional correctness is verified separately, through simulation, LVS, and design review.

Misconception: A "clean" DRC report (zero violations) means the design is ready for fabrication with no further review needed. Why it's wrong: DRC is one of several required checks. A design can pass DRC and still fail LVS (wrong connectivity), fail signal integrity analysis (crosstalk/reflections), or fail thermal analysis (hotspots) — none of which DRC evaluates. Correct understanding: A clean DRC report is necessary but not sufficient; it must be combined with LVS, signal integrity, and thermal checks (as applicable) before a design is truly ready for fabrication.

Misconception: DRC rules are universal — the same numeric limits apply to any PCB fabricator or any chip foundry. Why it's wrong: Every fabrication process has its own physical capabilities and limitations (a cheap 2-layer PCB house has much looser tolerances than a fine-pitch HDI board fabricator; different silicon foundry nodes have vastly different minimum feature sizes). Rules are tied to a specific process. Correct understanding: DRC must always be run against the correct, up-to-date rule deck for the exact fabrication process the design will actually use — using the wrong rule deck gives a false sense of security or unnecessarily rejects a perfectly manufacturable design.

Comparison and Connections

Check	What It Verifies	When It Runs	Typical Failure It Catches
ERC (Electrical Rule Check)	Schematic-level connectivity issues	During schematic capture	Unconnected pin, conflicting output drivers
DRC (Design Rule Check)	Physical/geometric/electrical manufacturability of the layout	After layout, before fabrication	Trace spacing violation, undersized via
LVS (Layout Versus Schematic)	Layout connectivity matches the intended schematic/netlist	After layout, alongside/after DRC	Accidental short or open introduced during layout
Signal Integrity Analysis	Electrical signal quality (reflections, crosstalk, timing)	After layout, on critical/high-speed nets	Ringing, crosstalk-induced errors

Practice Questions

Recall

1. Name the three broad categories of DRC rules. Guidance: Geometric rules, electrical rules, and manufacturing/process rules.

2. What is a "rule deck" and why must it match the specific fabrication process being used? Guidance: A rule deck is the complete set of numeric DRC limits for a specific process; each fabricator/foundry has different physical capabilities, so using the wrong rule deck gives inaccurate (too loose or too strict) results.

Understanding

3. Explain why DRC and LVS are described as complementary rather than redundant checks. Guidance: DRC checks whether the physical geometry is manufacturable (spacing, widths, current capacity) regardless of what circuit it implements; LVS checks whether that geometry's actual connectivity matches the intended schematic. A design could pass one and fail the other.

4. Why does DRC only check physical/manufacturing rules and not whether a circuit is functionally correct? Guidance: DRC operates on layout geometry and applies fixed rules from the fabrication process; it has no model of the circuit's intended behavior or specification, so functional correctness is verified separately via simulation and LVS.

Application

5. A DRC report flags a via as "below minimum drill size" for your chosen PCB fabricator. What are two possible ways to resolve this? Guidance: Increase the via's drill size to meet the minimum, or switch to a fabrication process/fabricator that supports smaller minimum drill sizes (if the smaller via is functionally necessary, e.g., for a fine-pitch BGA).

6. You're preparing a chip layout for a foundry with very tight minimum spacing rules compared to your previous project. What should you do before running your first DRC pass? Guidance: Load the correct, up-to-date rule deck for the new foundry/process node before running DRC — reusing the old project's rule deck would give misleading (too permissive) results.

Analysis

7. A board passes DRC with zero violations but fails in the field due to a trace overheating under load. What kind of check was likely missing or misconfigured, and why didn't DRC catch it? Guidance: Current-carrying capacity (electrical rule / trace-width-for-current check) was likely not configured or was insufficiently strict; DRC only flags what its configured rules check — if maximum current density rules weren't set for that specific net, an undersized trace can still pass DRC.

8. Compare the cost of fixing a DRC violation caught in software before fabrication versus after a batch of boards or chips has been manufactured. Guidance: Fixing a violation before fabrication costs a small amount of engineering time (edit and re-run DRC). After manufacturing, the same violation means scrapped units, wasted materials and assembly cost, and schedule delay for a re-spin — often orders of magnitude more expensive, especially for IC tape-outs.

FAQ

Is DRC only used for PCB design, or also for IC design? Both. DRC is used at every physical-layout stage of EDA — PCB layout tools run DRC against the PCB fabricator's rules, and IC layout tools run DRC against the semiconductor foundry's process design rules. The underlying concept (verify physical geometry against manufacturing limits) is identical; only the scale and specific rules differ.

Can DRC violations ever be safely ignored? Occasionally, yes — some flagged items are known false positives (e.g., a rule check that's overly conservative for a specific, deliberately designed structure) and experienced designers may explicitly waive them with documented justification. But every waived violation should be a deliberate, reviewed decision, never a default response to an inconvenient warning.

What happens if you skip DRC entirely and send a design straight to fabrication? You're gambling that your layout happens to comply with every relevant rule by luck or careful manual checking alone. In practice this frequently results in manufacturing defects, reduced yield, intermittent failures, or outright rejected orders — most professional fabricators actually require a DRC-clean design (or run their own DRC) before accepting a job.

How is DRC different for advanced IC process nodes versus older ones? Advanced nodes (very small feature sizes) have vastly more numerous and complex rules — accounting for lithography effects, density requirements, and multi-patterning constraints — making DRC computationally intensive and requiring far more careful rule configuration than older, larger-feature processes with simpler geometric constraints.

Does passing DRC guarantee good manufacturing yield? No — DRC guarantees the design meets the minimum rules the fabricator considers safe, but yield also depends on factors DRC doesn't directly control, like overall design robustness to process variation, testing coverage, and manufacturing process consistency itself. DRC compliance is necessary for good yield but not sufficient on its own.

Quick Revision

• DRC verifies a layout's physical geometry against a fabrication process's rules — it does not check functional correctness
• Rule categories: geometric (spacing/width), electrical (current density), manufacturing/process (layer thickness, materials)
• DRC workflow: design preparation → rule definition → execution → resolution → re-verification
• DRC is complementary to LVS: DRC checks "is this buildable?"; LVS checks "does this match the intended circuit?"
• A clean DRC report is necessary but not sufficient — signal integrity and thermal checks are still separately required
• Every fabrication process (PCB house or silicon foundry) has its own specific rule deck; using the wrong deck is a common, serious mistake
• Some DRC violations may be deliberately waived with documented justification, but never ignored by default
• Catching a DRC violation before fabrication costs minutes; catching it after manufacturing can mean scrapped units and schedule delay
• Advanced IC process nodes have far more numerous and complex DRC rules than older, larger-feature processes
• DRC improves manufacturability and yield but does not by itself guarantee good yield or functional correctness

Related Topics

Prerequisites: PCB Design, Layout Design, Schematic Capture

Related Topics: Signal Integrity, Thermal Analysis, Simulation and Verification

Next Topics: Signal Integrity, Thermal Analysis, EDA Tools and Software