5. Flip-Flops
Learning Objectives
- Define a flip-flop and explain how bistability allows it to store one bit
- Write the truth table and characteristic equation for SR, D, JK, and T flip-flops
- Explain the SR flip-flop's invalid state and how JK resolves it
- Distinguish level-triggered latches from edge-triggered flip-flops
- Explain how a D flip-flop is used for data storage and a T flip-flop for toggling
- Apply flip-flop behavior to trace output changes across several clock pulses
Quick Answer
A flip-flop is a bistable digital circuit — it has exactly two stable output states and can hold ("latch") one bit of information indefinitely until a triggering input tells it to change. Flip-flops are built from cross-coupled logic gates (NAND or NOR) whose feedback keeps the output stable even after the triggering input is removed. They matter because they are the smallest unit of digital memory: registers, counters, and RAM are all built by combining many flip-flops. The four common types — SR, D, JK, and T — differ only in how their inputs control which of the two states the output settles into.
How Flip-Flops Work
The core idea behind every flip-flop is feedback between two gates: gate 1's output feeds gate 2's input, and gate 2's output feeds back into gate 1's input. This creates two possible stable configurations, and the circuit will stay in whichever one it was last set to — that's what "bistable" means. A clock input, when present, restricts when the flip-flop is allowed to respond to its data inputs, which is what makes synchronous designs predictable.
SR Flip-Flop (Set-Reset)
The simplest flip-flop, built from two cross-coupled NOR gates (or NAND gates, depending on active-high or active-low design). It has two inputs, S (Set) and R (Reset).
| S | R | Q (next) | Description |
|---|---|---|---|
| 0 | 0 | Q (no change) | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Invalid | Both outputs forced equal — undefined |
Limitation: When S = R = 1 (for the NOR-based version), both Q and Q' are forced to 0, which violates the rule that Q and Q' must always be complements. This is the SR flip-flop's well-known invalid state.
JK Flip-Flop
The JK flip-flop fixes the SR flip-flop's invalid state by feeding Q and Q' back into the input logic, so that when J = K = 1, the flip-flop toggles instead of entering an undefined state.
| J | K | Q (next) | Description |
|---|---|---|---|
| 0 | 0 | Q (no change) | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q' (toggle) | Toggle |
Characteristic equation: Q(next) = JQ' + K'Q
D Flip-Flop (Data / Delay)
A D flip-flop has a single data input, D, and simply transfers that value to Q on the active clock edge — it "delays" the input by one clock cycle.
| D | Q (next) |
|---|---|
| 0 | 0 |
| 1 | 1 |
Characteristic equation: Q(next) = D. Because there is no "hold" ambiguity, D flip-flops are the most widely used type in registers and memory, since each one simply captures whatever value is on its D line at the clock edge.
T Flip-Flop (Toggle)
A T flip-flop has one input, T. When T = 1, the output toggles on each clock pulse; when T = 0, it holds its value. It is usually derived from a JK flip-flop by tying J and K together.
| T | Q (next) |
|---|---|
| 0 | Q (no change) |
| 1 | Q' (toggle) |
Characteristic equation: Q(next) = T ⊕ Q. This toggle behavior is exactly what makes T flip-flops the natural building block of binary counters — each toggle divides the input clock frequency by 2.
Latches vs Edge-Triggered Flip-Flops
A latch is level-triggered — it follows its input as long as an enable signal is high, and can change output multiple times while enabled. A true flip-flop is edge-triggered — it samples its input only at the exact moment the clock transitions (rising or falling edge) and ignores input changes at all other times. Edge-triggering is what makes multi-flip-flop circuits like counters and shift registers behave predictably, because every flip-flop updates at the same clock instant rather than continuously reacting to its neighbors.
Real-World Example
Inside a digital wristwatch, a chain of T flip-flops (each toggling on the previous one's output) divides down a fast crystal oscillator frequency (commonly 32,768 Hz) step by step until it produces a clean 1 Hz pulse used to advance the seconds counter — 15 successive toggle stages exactly divide 32,768 by 2 fifteen times to reach 1 Hz.
Common Misunderstanding
Students often think "D flip-flop" means it has some kind of built-in delay circuit (like an RC timer). In reality, "D" stands for "Data," and the only delay is the natural one clock-cycle lag between when data is presented on D and when it appears on Q — there's no analog timing component involved.
Key Terms
| Term | Definition | Related Concept |
|---|---|---|
| Bistable | Having exactly two stable output states | Flip-flop foundation |
| SR flip-flop | Basic flip-flop with Set and Reset inputs; has an invalid state at S=R=1 | Cross-coupled NOR/NAND gates |
| JK flip-flop | Flip-flop that toggles when J=K=1, eliminating the SR invalid state | Feedback of Q, Q' |
| D flip-flop | Flip-flop that transfers its data input to Q at the clock edge | Registers, memory |
| T flip-flop | Flip-flop that toggles output when T=1 | Binary counters |
| Latch | A level-triggered memory element, active while enable is high | Level triggering |
| Edge-triggered | Responding to input only at a clock transition, not the whole level | Synchronous design |
| Characteristic equation | A Boolean expression giving the next state as a function of inputs and present state | Flip-flop analysis |
Common Mistakes
Misconception: SR = R = 1 is just another valid "hold" state for the SR flip-flop. Why it's wrong: Setting both S and R to 1 in a NOR-based SR flip-flop forces both Q and Q' to 0 simultaneously, breaking the rule that they must always be complementary outputs, and the result when the inputs return to 0,0 becomes unpredictable. Correct understanding: S=R=1 is the forbidden/invalid input combination for the SR flip-flop; designers avoid it entirely or use a JK flip-flop, which handles this case safely by toggling instead.
Misconception: A latch and a flip-flop are just two names for the same thing. Why it's wrong: A latch is level-triggered and can change output any time its enable is active, which can cause multiple unwanted transitions ("glitches") if the data input is noisy. A flip-flop only samples input at a clock edge. Correct understanding: Use "latch" only for level-triggered devices and "flip-flop" for edge-triggered devices — the distinction matters enormously for timing analysis in real circuits.
Misconception: A T flip-flop is a fundamentally different, independent circuit type from a JK flip-flop. Why it's wrong: A T flip-flop is simply a JK flip-flop with its J and K inputs tied together — when J=K=0 it holds, when J=K=1 it toggles, matching the T=0/T=1 behavior exactly. Correct understanding: T flip-flops are usually built from JK flip-flops (or D flip-flops with XOR feedback) rather than manufactured as a separate primitive gate structure.
Comparison and Connections
| Flip-Flop | Inputs | Holds when | Toggles when | Typical Use |
|---|---|---|---|---|
| SR | S, R | S=0, R=0 | Never (S=R=1 is invalid) | Simple memory, basic latches |
| JK | J, K | J=0, K=0 | J=1, K=1 | General-purpose sequential logic |
| D | D | Never (always follows D) | Never | Registers, memory, pipelining |
| T | T | T=0 | T=1 | Counters, frequency dividers |
Practice Questions
Recall
-
What are the two stable states of a flip-flop called collectively? Bistable states — the flip-flop can rest indefinitely in either state until triggered to change.
-
What input combination is invalid for an SR flip-flop, and why? S=1, R=1 for a NOR-based SR flip-flop, because it forces both Q and Q' to 0, violating the requirement that they be complementary.
Understanding
-
Explain how the JK flip-flop avoids the invalid state that the SR flip-flop has. The JK flip-flop feeds Q and Q' back into the gating logic so that when J=K=1, the circuit sees its own current state and flips it (toggles) rather than forcing an undefined output.
-
Why is the D flip-flop the most common choice in registers and memory chips? Because it has no hold ambiguity or invalid state — it simply captures whatever value is on D at the clock edge, making its behavior completely predictable and simple to control with just one data line per bit.
Application
-
You need to build a circuit that divides an input clock frequency by 2. Which flip-flop type is the natural choice, and how should its input be connected? A T flip-flop with T tied permanently to 1 (or a JK flip-flop with J=K=1). Each clock pulse toggles the output, so the output changes state at half the input clock's frequency.
-
A shift register needs each stage to simply pass along whatever bit its neighbor is holding, on every clock edge. Which flip-flop type should each stage use? A D flip-flop — its D input is connected to the Q output of the previous stage, so each clock edge shifts the bit pattern one position along the chain.
Analysis
-
A JK flip-flop starts at Q=0. It receives the following (J,K) pairs on successive clock edges: (1,0), (1,1), (1,1), (0,1). Trace the value of Q after each edge. Start Q=0. (1,0)=Set → Q=1. (1,1)=Toggle → Q=0. (1,1)=Toggle → Q=1. (0,1)=Reset → Q=0. Final Q=0.
-
Compare a level-triggered latch and an edge-triggered flip-flop in a circuit where the data input is noisy (glitching) while the enable/clock signal is high. Which device is more likely to capture the wrong value, and why? The level-triggered latch is far more vulnerable, because it continues to follow the D input the entire time enable is high, so any glitch during that window changes its output. The edge-triggered flip-flop only samples the input at the single instant of the clock edge, ignoring glitches at other times.
FAQ
Why does the SR flip-flop have an invalid state but the JK doesn't? The SR flip-flop has no way to interpret S=R=1 safely because both feedback paths force their outputs low simultaneously. The JK flip-flop resolves this by using the flip-flop's own current output as part of the input logic, so J=K=1 has a well-defined meaning: toggle.
What does "edge-triggered" actually mean in circuit terms? It means the flip-flop only updates its stored value during the brief transition of the clock signal (rising edge, typically 0-to-1, or falling edge, 1-to-0) — for the rest of the clock period, changes on the data input have no effect on the output.
Can a D flip-flop be built from a JK flip-flop? Yes — connect the D input directly to J, and connect an inverted version of D to K. This forces the flip-flop to always Set when D=1 and Reset when D=0, exactly matching D flip-flop behavior.
Why are flip-flops sometimes called "the atoms of digital memory"? Because each one stores exactly one bit and cannot be subdivided further while remaining a functional memory unit — every larger memory structure (registers, counters, RAM cells built from flip-flop-like circuits) is fundamentally an array of these single-bit storage elements.
What happens if a flip-flop's setup or hold time is violated? If the data input changes too close to the clock edge (violating setup or hold time specifications), the flip-flop can enter a temporary unstable condition called metastability, where its output takes an unpredictable amount of time to settle to a valid 0 or 1 — a serious concern in high-speed digital design.
Quick Revision
- A flip-flop is bistable: it stores 1 bit by holding one of two stable states
- SR flip-flop: Set (S=1,R=0), Reset (S=0,R=1), Hold (S=R=0); S=R=1 is invalid
- JK flip-flop: same as SR but J=K=1 causes toggle instead of an invalid state
- D flip-flop: Q(next) = D — simplest and most common for registers
- T flip-flop: Q(next) = T⊕Q — toggles when T=1, ideal for counters
- Latches are level-triggered; true flip-flops are edge-triggered
- T flip-flops are usually built from JK flip-flops with J and K tied together
- Setup/hold time violations can cause metastability in real circuits
Related Topics
Prerequisites: Logic gates, sequential circuits and feedback, clock signals
Related Topics: Latches, characteristic equations, timing diagrams, metastability
Next Topics: Counters (built from toggling flip-flops), registers (built from D flip-flops)