Sequential Circuits
Learning Objectives
- Explain why a sequential circuit's output depends on both current inputs and stored past state.
- Distinguish a latch from a flip-flop, and explain what "clocked" and "edge-triggered" mean.
- Compare SR, D, JK, and T flip-flops by what each one does and where each is typically used.
- Trace a flip-flop's output across several clock edges given a sequence of inputs.
- Explain how flip-flops combine to build counters and finite state machines (FSMs).
Quick Answer
A sequential circuit is a digital circuit whose output depends not only on its current inputs but also on what has happened before — it has memory. This is the opposite of a combinational circuit, which only ever looks at the present. Sequential circuits are built from memory elements called latches and flip-flops, most of which are synchronized by a clock signal that determines exactly when stored values are allowed to update. Sequential circuits matter because memory is what makes computing possible: registers, counters, RAM, and entire processors' control logic are sequential circuits. Without them, a digital system could compute a result but could never store it, count anything, or remember what state it's in — which means no loops, no counters, and no stored data of any kind.
What Gives a Circuit Memory
The test for "sequential" is the mirror image of the test for "combinational": if the same inputs can produce different outputs depending on what happened earlier, the circuit is sequential. That "what happened earlier" is stored as the circuit's state, held in one or more memory elements.
Almost all practical sequential circuits are synchronous — they use a clock signal (a periodic 0/1 wave) to control exactly when the stored state is allowed to change. Between clock transitions, the stored value stays frozen no matter how the inputs wiggle; only at the clock edge does the circuit "look" at its inputs and decide whether to update. This discipline is what makes large sequential systems predictable: without it, tiny timing differences between components could cause chaotic, inconsistent behavior.
Latches vs. Flip-Flops
These two terms are often used loosely, but there's a real distinction:
- A latch is level-triggered: it stores whatever value is on its input for as long as an enable signal stays high. It reacts continuously while enabled.
- A flip-flop is edge-triggered: it only captures the input value at the instant the clock transitions (e.g., from 0 to 1, a "rising edge"), and ignores the input the rest of the time.
Flip-flops are used far more often in synchronous digital design because edge-triggering avoids the timing hazards that come from a latch reacting continuously while enabled.
The SR Latch (Set-Reset)
The SR latch is the simplest memory element, built from two cross-coupled NOR (or NAND) gates. It has two inputs, Set (S) and Reset (R), and stores one bit as output Q.
| S | R | Q (next state) | Meaning |
|---|---|---|---|
| 0 | 0 | Q (unchanged) | Hold current value |
| 0 | 1 | 0 | Reset — force Q to 0 |
| 1 | 0 | 1 | Set — force Q to 1 |
| 1 | 1 | Invalid | Forbidden — undefined output |
Real-world example: the SR latch behaves like a light switch that only responds to two separate "on" and "off" buttons rather than a single toggle — pressing "off" (R=1) always turns the light off regardless of its current state, and leaving both buttons unpressed just leaves the light exactly as it was.
Why it matters: the SR latch is the conceptual ancestor of every other flip-flop — it demonstrates the core idea of feedback creating memory, which every more advanced design builds on.
Common misunderstanding: students often think S=1, R=1 just "does both" (sets and resets simultaneously). It doesn't — it's explicitly forbidden because it creates a contradiction in the underlying feedback loop, leaving the output in an unpredictable, unstable state.
The D Flip-Flop
The D (Data) flip-flop is the most widely used flip-flop in modern digital design. It has one data input (D), a clock input, and stores whatever value was on D at the last rising clock edge.
| Clock edge | D | Q (after edge) |
|---|---|---|
| rising | 0 | 0 |
| rising | 1 | 1 |
| (no edge) | X (any) | unchanged |
Real-world example: a D flip-flop is exactly what a single bit of a CPU register is built from — a 32-bit register is just 32 D flip-flops sharing one clock line, each storing one bit of the register's value.
Why it matters: the D flip-flop eliminates the SR latch's forbidden state entirely (there's only one data input, so there's no way to create a contradictory command), which is a major reason it replaced SR-style designs in most modern circuits.
Common misunderstanding: students sometimes think Q updates the instant D changes. It doesn't — Q only updates at the clock edge, no matter how many times D changes in between. This is precisely what makes it useful as a stable storage element.
The JK Flip-Flop
The JK flip-flop behaves like an SR flip-flop but fixes the forbidden-state problem: when both inputs are 1, instead of being invalid, it toggles the output.
| J | K | Q (next state) |
|---|---|---|
| 0 | 0 | Q (unchanged) |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | Toggle (flip Q) |
Real-world example: JK flip-flops are a natural fit for binary counters, since counting essentially means "toggle this bit every time the lower bit rolls over" — precisely the J=K=1 behavior.
Why it matters: the JK flip-flop is the most flexible of the classic flip-flop types because it can be configured (by tying J and K together) to behave exactly like a T flip-flop, or (by controlling J and K independently) like an SR flip-flop without the invalid state.
Common misunderstanding: people sometimes assume JK stands for something meaningful, like initials of inputs "Just" and "Keep." It's simply a naming convention (the letters were chosen to avoid confusion with S and R when the JK flip-flop was introduced as a fix for the SR latch's invalid state) — it has no deeper technical meaning.
The T Flip-Flop (Toggle)
The T flip-flop has a single input, T. When T=1, the output toggles on each clock edge; when T=0, the output holds its value.
| T | Q (next state) |
|---|---|
| 0 | Q (unchanged) |
| 1 | Toggle (flip Q) |
Real-world example: a T flip-flop is the natural building block of a binary counter — chain several together, each one toggling on every rising edge of the previous stage's output, and you get a circuit that counts in binary automatically.
Why it matters: the T flip-flop's simplicity (one input, one behavior) makes counter circuits easy to design and reason about, compared to wiring up SR or JK flip-flops to achieve the same toggle behavior manually.
Counters and Finite State Machines
Chaining flip-flops together produces circuits with much richer behavior than any single flip-flop:
- A counter is a chain of flip-flops (commonly T or JK) arranged so the stored value increments (or decrements) on each clock pulse. A 4-bit binary counter cycles through 0000 up to 1111 and then wraps back to 0000.
- A finite state machine (FSM) generalizes this idea: it's a circuit with a fixed number of states, and on each clock edge it moves ("transitions") from its current state to a next state, determined by the current state and the current inputs. Traffic light controllers, vending machine logic, and CPU control units are all commonly designed as FSMs.
The key insight connecting all of this back to the flip-flop level: an FSM's "state" is literally just the combined value stored in a group of flip-flops, and its "transition logic" is combinational logic that computes the next state from the current state and inputs.
Visualizing State Transitions
Key Terms
| Term | Definition |
|---|---|
| Sequential circuit | A circuit whose output depends on current inputs and stored past state (memory). |
| State | The stored information a sequential circuit holds between clock cycles. |
| Clock signal | A periodic signal that synchronizes when sequential circuits are allowed to update their state. |
| Latch | A level-triggered memory element that stores its input continuously while an enable signal is active. |
| Flip-flop | An edge-triggered memory element that captures its input only at a clock transition. |
| SR latch | The simplest latch, with Set and Reset inputs; has a forbidden input combination. |
| D flip-flop | A flip-flop that stores whatever value is on its data input at the clock edge. |
| JK flip-flop | A flip-flop that fixes the SR latch's forbidden state by toggling when both inputs are 1. |
| T flip-flop | A flip-flop with a single toggle input; flips its output on each clock edge when T=1. |
| Counter | A chain of flip-flops arranged to increment or decrement a stored binary value each clock pulse. |
| Finite state machine (FSM) | A sequential circuit modeled as a fixed set of states with defined transitions between them. |
Common Mistakes
Misconception 1: "A latch and a flip-flop are just two names for the same thing." Why it's wrong: Both store one bit, so the distinction seems unimportant at first glance. Correct: A latch is level-triggered (reacts continuously whenever enabled), while a flip-flop is edge-triggered (reacts only at a clock transition). This difference matters enormously in real circuits, since edge-triggering avoids race conditions that level-triggered latches are prone to in synchronous systems.
Misconception 2: "SR = 1,1 is fine because it just means 'both set and reset happen.'" Why it's wrong: Because S and R look like independent, combinable controls, students expect the circuit to handle both simultaneously. Correct: Setting both inputs high drives the SR latch's internal feedback loop into a contradiction, leaving the output undefined (and dependent on manufacturing variation or timing when both inputs are released). This is why SR=1,1 is explicitly documented as forbidden, not just unusual.
Misconception 3: "A JK flip-flop with J=K=1 is unpredictable, just like SR with S=R=1." Why it's wrong: Because JK was designed specifically to patch the SR latch's flaw, it's easy to assume the fix is incomplete or inconsistent. Correct: J=K=1 is fully defined — it deterministically toggles the output on every clock edge. This is precisely the improvement JK flip-flops made over SR latches: every input combination has a well-defined result.
Comparison and Connections
| Flip-Flop | Inputs | Behavior when both/relevant inputs are active | Typical Use |
|---|---|---|---|
| SR | Set, Reset | Forbidden (undefined) | Basic memory element, teaching |
| D | Data | N/A (only one data input) | Registers, general storage |
| JK | J, K | Toggle | Counters, general-purpose sequential logic |
| T | Toggle | Toggle | Binary counters |
| Concept | Combinational Circuit | Sequential Circuit |
|---|---|---|
| Depends on | Current inputs only | Current inputs + stored past state |
| Needs a clock? | No | Usually yes |
| Has memory? | No | Yes |
| Example | Adder, MUX | Flip-flop, counter, register, FSM |
Practice Questions
Recall
- What are the two inputs of an SR latch, and what does each one do? Answer guidance: Set (S) forces the output to 1; Reset (R) forces the output to 0.
- What is the single input of a T flip-flop, and what happens when it's 1 at a clock edge? Answer guidance: T (toggle); when T=1 at a clock edge, the flip-flop's output flips to the opposite value.
Understanding
- Explain why the D flip-flop has no forbidden input combination, while the SR latch does. Answer guidance: The D flip-flop has only one data input, so there's no way to issue two contradictory commands (like "set" and "reset") at once — the circuit simply copies D to Q at the clock edge, which is always well-defined.
- Why do most sequential circuits use edge-triggered flip-flops rather than level-triggered latches? Answer guidance: Edge-triggering restricts state changes to a single instant per clock cycle, avoiding the race conditions and unpredictable multiple updates that can occur when a level-triggered latch reacts continuously while enabled.
Application
- You need to build a 3-bit binary counter. Which flip-flop type is most naturally suited, and why? Answer guidance: T (or JK configured as T, with J=K=1) flip-flops, because counting requires each bit to toggle based on the state of the lower-order bit — exactly the toggle behavior these flip-flops provide.
- A D flip-flop currently holds Q=0. D is set to 1, but no clock edge occurs yet. What is Q right now? Answer guidance: Q remains 0 — a flip-flop only updates its stored value at a clock edge, so changes to D before the edge have no effect on Q yet.
Analysis
- A student argues: "Since a JK flip-flop can do everything an SR latch can do, plus more, there's never a reason to use an SR latch." Evaluate this claim. Answer guidance: Largely true for modern synchronous design — JK (and D) flip-flops are generally preferred because they avoid the SR latch's undefined state. However, the SR latch (or its NAND/NOR gate implementation) remains pedagogically important and appears in simple asynchronous control or debouncing circuits where its simplicity is sufficient.
- Compare a counter and a general finite state machine (FSM). Is every counter an FSM? Is every FSM a counter? Answer guidance: Every counter is a specific, simple type of FSM (one where the "transition logic" always just increments/decrements). Not every FSM is a counter — general FSMs can have arbitrary, non-sequential transition rules (e.g., a vending machine's states don't simply count up by one each cycle).
FAQ
Q: Why do sequential circuits need a clock at all? A: A clock ensures every flip-flop in a large circuit updates at the same, predictable instant. Without it, tiny differences in wire length and gate delay could cause different parts of the circuit to update at slightly different times, leading to inconsistent or corrupted stored values.
Q: Can a sequential circuit exist without any flip-flops? A: Not quite — but you can build memory purely from combinational gates arranged in a feedback loop (like the SR latch, which uses only NOR or NAND gates). That still counts as sequential, because a feedback loop introduces state, even without a dedicated "flip-flop" component. It's just not clocked.
Q: What's the practical difference between a register and a single flip-flop? A: A single flip-flop stores one bit. A register is simply multiple flip-flops (commonly D flip-flops) sharing a common clock, storing multiple bits as a single, wider value — for example, a 32-bit register is 32 D flip-flops.
Q: How is a finite state machine different from a regular sequential circuit? A: Every FSM is a sequential circuit, but "FSM" specifically emphasizes the abstract model — a defined set of named states and transition rules — rather than the electrical implementation. It's a design-level way of thinking about sequential behavior before you commit to specific flip-flops and gates.
Q: Why does the SR latch's forbidden state matter if I'd never intentionally set both inputs to 1? A: In real circuits, brief unintended pulses (glitches) or race conditions can accidentally drive both inputs high momentarily, especially at power-up. Because that state is undefined, the outcome is not just "wrong" but unpredictable and inconsistent across identical chips — which is precisely why designers avoid using bare SR latches in situations where this could happen.
Quick Revision
- Sequential circuits have memory: output depends on current inputs and stored past state.
- A clock signal synchronizes exactly when sequential circuits are allowed to update their state.
- Latches are level-triggered (react while enabled); flip-flops are edge-triggered (react only at a clock edge).
- SR latch: Set=1 forces Q=1, Reset=1 forces Q=0, S=R=1 is forbidden (undefined).
- D flip-flop: stores whatever is on D at the clock edge; no forbidden state; basis of registers.
- JK flip-flop: like SR but J=K=1 toggles the output instead of being undefined.
- T flip-flop: single toggle input; flips output on each clock edge when T=1; ideal for counters.
- Counters are chains of flip-flops that increment/decrement a stored value each clock pulse.
- A finite state machine (FSM) is a sequential circuit modeled as states with defined transitions; a counter is a simple special case of an FSM.
- An FSM's "state" is literally the value stored in its flip-flops; its "next-state logic" is combinational.
- Registers, RAM, counters, and CPU control units are all built from these flip-flop building blocks.
Related Topics
Prerequisites: 1. Introduction to Digital Logic, 2. Combinational Circuits.
Related Topics: Registers, RAM design, clock domains and timing, finite automata (theory of computation).
Next Topics: 4. Digital Design Tools